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rev. 1.0 6/12 copyright ? 2012 by silicon laboratories SI515 v oltage -c ontrolled c rystal o scillator (vcxo) 100 kh z to 250 mh z features applications description the SI515 vcxo utilizes silicon labor atories' advanced pll technology to provide any frequency from 100 khz to 25 0 mhz. unlike a traditional vcxo where a different crystal is r equired for each output frequency , the SI515 uses one fixed crystal and silicon labs? proprietary synthesizer to generate any frequency across this range. this ic-based approach allo ws the crystal resonator to provide enhanced reliability, improved mechanical robustness, and excellent stability. in addition, this solution provides superio r control voltage linearity and supply noise rejection, improving pll stability and si mplifying low jitter pll design in noisy environments. the SI515 is factory-c onfigurable for a wide variety of user specifications, including frequency, supply vo ltage, output format, tuning slope and stability. specific configurations are factory-programmed at time of shipment, eliminating long lead times and non-recurr ing engineering charges associated with custom frequency oscillators. functional block diagram ? supports any frequency from 100 khz to 250 mhz ? low-jitter operation ? short lead times: <2 weeks ? at-cut fundamental mode crystal ensures high reliability/low aging ? high power supply noise rejection ? 1% control voltage linearity ? available cmos, lvpecl, lvds, and hcsl outputs ? optional integrated 1:2 cmos fanout buffer ? 3.3 and 2.5 v supply options ? industry-standard 3.2 x 5.0 mm and 5 x 7 mm package/pinouts ? pb-free/rohs-compliant ? selectable kv (60, 90, 120, 150 ppm/v) ? sonet/sdh/otn ? pon ? low jitter plls ? xdsl ? broadcast video ? te l e c o m ? switches/routers ? fpga/asic clock generation v dd any-frequency 0.1 to 250 mhz clock synthesis fixed frequency oscillator clk+ clk? gnd vc adc power supply filtering oe ordering information: see page 14. pin assignments: see page 12. si5602 1 2 3 6 5 4 v dd clk? clk+ gnd oe vc lvpecl/lvds/hcsl/ dual cmos vcxo 1 2 3 6 5 4 v dd nc clk gnd oe vc cmos vcxo SI515
SI515 2 rev. 1.0
SI515 rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1. dual cmos buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4. package outline diagram: 5 x 7 mm, 6- pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. pcb land pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 6. package outline diagram: 3. 2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7. pcb land pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.1. SI515 top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2. top marking explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
SI515 4 rev. 1.0 1. electrical specifications table 1. recommended operating conditions v dd = 2.5 or 3.3 v 10%, t a = ?40 to +85 o c parameter symbol test condition min typ max unit supply voltage v dd 3.3 v option 2.97 3.3 3.63 v 2.5 v option 2.25 2.5 2.75 v supply current i dd cmos, 100 mhz, single-ended ?2429ma lvds (output enabled) ?2226ma lvpecl (output enabled) ?4246ma hcsl (output enabled) ?4447ma tristate (output disabled) ??22ma oe ?1? setting v ih see note 0.80 x v dd ??v oe ?0? setting v il see note ? ? 0.20 x v dd v oe internal pull-up/ pull-down resistor * r i ?45?k ? operating temperature t a ?40 ? 85 o c *note: active high and active low polarity oe options available. acti ve high uses internal pull-up. active low uses internal pull- down. see ordering information on page 13.
SI515 rev. 1.0 5 table 2. vc control voltage input v dd = 2.5 or 3.3 v 10%, t a = ?40 to +85 o c parameter symbol test condition min typ max unit control voltage range v c 0.1 x v dd v dd /2 0.9 x v dd v control voltage tuning slope (10 to 90% v dd ) kv positive slope, ordering option 60, 90, 120, 150 ppm/v kv variation kv_var ? ? 10 % control voltage linearity l vc bsl ?5 1 +5 % modulation bandwidth bw ? 10 ? khz vc input impedance z vc ?100?k ? table 3. output clock frequency characteristics v dd = 2.5 or 3.3 v 10%, t a = ?40 to +85 o c parameter symbol test condition min typ max unit nominal frequency f o cmos, dual cmos 0.1 ? 212.5 mhz f o lvds/lvpecl/hcsl 0.1 ? 250 mhz temperature stability s t t a = ?40 to +85 o c ?20 ? +20 ppm aging a frequency drift over 10 year life ? ? 8.5 ppm minimum absolute pull range apr ordering option 30, 50,80, 100 ppm startup time t su minimum v dd to output fre- quency (f o ) within specification ??10ms disable time t d f o ?? 10 mhz ? ? 5 s f o <10mhz 40 s enable time t e f o ? 10 mhz ? ? 20 s f o <10mhz 60 s
SI515 6 rev. 1.0 table 4. output clock levels and symmetry v dd = 2.5 or 3.3 v 10%, t a = ?40 to +85 o c parameter symbol test condition min typ max unit cmos output logic high v oh 0.85 x v dd ??v cmos output logic low v ol ? ? 0.15 x v dd v cmos output logic high drive i oh 3.3 v ?8 ? ? ma 2.5 v ?6 ? ? ma cmos output logic low drive i ol 3.3 v 8 ? ? ma 2.5 v 6 ? ? ma cmos output rise/fall time (20 to 80% v dd ) t r /t f 0.1 to 125 mhz, c l = 15 pf ?0.81.2ns 0.1 to 212.5 mhz, c l = no load ?0.60.9ns lvpecl/hcsl output rise/fall time (20 to 80% v dd ) t r /t f ??565ps lvds output rise/fall time (20 to 80% v dd ) t r /t f ??800ps lvpecl output common mode v oc 50 ? to v dd ? 2 v, single-ended ? v dd ? 1.4 v ?v lvpecl output swing v o 50 ? to v dd ? 2 v, single-ended 0.55 0.8 0.90 v ppse lvds output common mode v oc 100 ? line-line, v dd = 3.3/2.5 v 1.13 1.23 1.33 v lvds output swing v o single-ended 100 ?? differential termination 0.25 0.38 0.42 v ppse hcsl output common mode v oc 50 ?? to ground 0.35 0.38 0.42 v hcsl output swing v o single-ended 0.58 0.73 0.85 v ppse duty cycle dc 48 50 52 %
SI515 rev. 1.0 7 table 5. output clock jitter and phase noise (lvpecl) v dd = 2.5 or 3.3 v 10%, t a = ?40 to +85 o c; output format = lvpecl parameter symbol test condition min typ max unit period jitter (rms) j prms 10 k samples 1 ??1.3 ps period jitter (pk-pk) j ppkpk 10 k samples 1 ??11 ps phase jitter (rms) j 12 khz to 20 mhz 2 (brickwall) ? 0.9 1.3 ps 1.875 mhz to 20 mhz 2 (brickwall) ? 0.25 0.5 ps phase noise, 155.52 mhz n 100 hz offset ? ?71 ? dbc/hz 1 khz offset ? ?93 ? dbc/hz 10 khz offset ? ?113 ? dbc/hz 100 khz offset ? ?124 ? dbc/hz 1 mhz offset ? ?136 ? dbc/hz additive rms jitter due to external power supply noise 3 j psrr 100 khz sinusoidal noise ? 4.0 ? ps 200 khz sinusoidal noise ? 3.5 ? ps 500 khz sinusoidal noise ? 3.5 ? ps 1 mhz sinusoidal noise ? 3.5 ? ps spurious performance spr f o =156.25mhz, offset > 10 khz ??75? dbc notes: 1. applies to output frequencies: 74.17 582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 mhz. 2. applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155. 52, 156.25, 212.5, 250 mhz. 3. 156.25 mhz. increase in jitter on output clock due to s purs introduced by sinewave noise added to vdd (100 mv pp ).
SI515 8 rev. 1.0 table 6. output clock jitter and phase noise (lvds) v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c; output format = lvds parameter symbol test condition min typ max unit period jitter (rms) jprms 10k samples 1 ??2.1ps period jitter (pk-pk) jppkpk 10k samples 1 ??18ps phase jitter (rms) j 1.875 mhz to 20 mhz integration bandwidth 2 (brickwall) ?0.250.55ps 12 khz to 20 mhz integration band- width 2 (brickwall) ?0.81.1ps phase noise, 156.25 mhz n100hz ??72?dbc/hz 1khz ? ?93 ? dbc/hz 10 khz ? ?114 ? dbc/hz 100 khz ? ?123 ? dbc/hz 1 mhz ? ?136 ? dbc/hz spurious spr lvpecl output , 156.25 mhz, offset>10 khz ??75?dbc notes: 1. applies to output frequencies: 74.17 582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 mhz. 2. applies to output frequencies: 100 , 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 mhz.
SI515 rev. 1.0 9 table 7. output clock jitter and phase noise (hcsl) v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c; output format = hcsl parameter symbol test condition min typ max unit period jitter (rms) jprms 10k samples * ??1.2ps period jitter (pk-pk) jppkpk 10k samples * ??11ps phase jitter (rms) j 1.875 mhz to 20 mhz integration bandwidth * (brickwall) ?0.250.30ps 12 khz to 20 mhz integration band- width * (brickwall) ?0.81.0ps phase noise, 156.25 mhz n100hz ??75?dbc/hz 1khz ? ?98 ? dbc/hz 10 khz ? ?117 ? dbc/hz 100 khz ? ?127 ? dbc/hz 1 mhz ? ?136 ? dbc/hz spurious spr lvpecl output , 156.25 mhz, offset>10 khz ??75?dbc *note: applies to an output frequency of 100 mhz.
SI515 10 rev. 1.0 table 8. output clock jitter and phase noise (cmos, dual cmos) v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c; output format = cmos, dual cmos parameter symbol test condition min typ max unit phase jitter (rms) j 1.875 mhz to 20 mhz integration bandwidth 2 (brickwall) ?0.250.35ps 12 khz to 20 mhz integration band- width 2 (brickwall) ?0.81.1ps phase noise, 156.25 mhz n100hz ??71?dbc/hz 1khz ? ?93 ? dbc/hz 10 khz ? ?113 ? dbc/hz 100 khz ? ?123 ? dbc/hz 1 mhz ? ?136 ? dbc/hz spurious spr lvpecl output , 156.25 mhz, offset>10 khz ??75?dbc notes: 1. applies to output frequencies: 74.17 582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 mhz. 2. applies to output frequencies: 100, 106.25, 1 25, 148.35165, 148.5, 150, 15 5.52, 156.25, 212.5 mhz. table 9. environmental compliance and package information parameter conditions/test method mechanical shock mil-std-883, method 2002 mechanical vibration mil-std-883, method 2007 solderability mil-std -883, me thod 2003 gross and fine leak mil-std-883, method 1014 resistance to solder heat mil-std-883, method 2036 moisture sensitivity level msl 1 contact pads gold over nickel
SI515 rev. 1.0 11 table 10. thermal characteristics parameter symbol test condition value unit thermal resistance junction to ambient ? ja still air 110 c/w table 11. absolute maximum ratings 1 parameter symbol rating unit maximum operating temperature t amax 85 o c storage temperature t s ?55 to +125 o c supply voltage v dd ?0.5 to +3.8 v input voltage (any input pin) v i ?0.5 to v dd + 0.3 v esd sensitivity (hbm, per jesd22-a114) hbm 2 kv soldering temperature (pb-free profile) 2 t peak 260 o c soldering temperature time at t peak (pb-free profile) 2 t p 20?40 sec notes: 1. stresses beyond those listed in this table may cause pe rmanent damage to the device. functional operation or specification compliance is not impli ed at these conditions. exposure to ma ximum rating conditions for extended periods may affect device reliability. 2. the device is compliant with jedec j-std-020.
SI515 12 rev. 1.0 2. pin descriptions table 12. SI515 pin descriptions (cmos) pin name cmos function 1 v c control voltage input. 2 oe output enable. internal pull-up for oe active high. pull- down for oe active low. see ordering information. 3 gnd electrical and case ground. 4 clk clock output. 5 nc no connect. make no external connection to this pin. 6 v dd power supply voltage. table 13. SI515 pin description s (lvpecl/lvds/hcsl/dual cmos) pin name lvpecl/lvds/hcsl/du al cmos function 1 v c control voltage input. 2 oe output enable. internal pull-up for oe active high. pull- down for oe active low. see ordering information. 3 gnd electrical and case ground. 4 clk+ clock output. 5 clk? complementary clock output. 6 v dd power supply voltage. 1 2 3 6 5 4 v dd clk? clk+ gnd oe vc lvpecl/lvds/hcsl/ dual cmos vcx o 1 2 3 6 5 4 v dd nc clk gnd oe vc cmos vcxo
SI515 rev. 1.0 13 2.1. dual cmos buffer dual cmos output format ordering options support either complementary or in-phase output signals. this feature enables replacement of multiple vcxos with a single SI515 device. figure 1. integrated 1:2 cmos buffer supports complementary or in-phase outputs ~ ~ complementary outputs in-phase outputs
SI515 14 rev. 1.0 3. ordering information the SI515 supports a variety of opti ons including frequency, stability, tuning slope, output format, and v dd . specific device configurations are programmed into the SI515 at ti me of shipment. configuratio ns are specified using the part number configuration chart shown below. silicon labs provi des a web browser- based part number configuration utility to simplif y this process. refer to www.silabs.com/vcxopartnumber to access this tool. the SI515 vcxo series is supplied in industry-standar d, rohs compliant, lead-free, 3.2 x 5.0 mm and 5 x 7 mm packages. tape and reel packaging is an ordering option. figure 2. part number convention example ordering part number: 515bbb212m500bagr. the series prefix, 515, indicates the device is a single frequency vcxo. the 1st option code b specifies the output format is lvds and powered from a 3.3 v supply. the stability and apr code b indicates a temperature stabilit y of 20 ppm with a tuning slope of 120 ppm/v. the 3rd option code b specifies the oe pin is active low. the frequency code is 212m500. per this convention, and as indicated by the part number lookup utility at www.silabs.com/vcxopartnumber, the output frequency is 212.5 mhz. the package code b refers to the 3.2 x 5 mm footprint with six pins. the la st a refers to the product revision, g indicates the temperature range (?40 to +85 c), and r specifies the device ships in tape and reel format. note: cmos and dual cmos maximum frequency is 212.5 mhz. series output format package 515 single frequency vcxo lvpecl, lvds, hcsl, cmos, dual cmos 6-pin a = revision: a g = temp range: -40c to 85c r = tape & reel; blank = trays. x x 515 x xxxmxxx x 1 st option code: output format vdd output format a 3.3v lvpecl agr x x 515 x xxxmxxx x b3.3v lvds c3.3v cmos d 3.3v hcsl e 2.5v lvpecl agr package option dimensions a 5x7mm f2.5v lvds g2.5v cmos h 2.5v hcsl m 3.3v dual cmos (in-phase) 3 rd option code: output enable oe polarity a oe active high 2 nd option code: stability & apr a 5 x 7 mm b 3.2 x 5 mm n 3.3v dual cmos (complementary) p 2.5v dual cmos (in-phase) q 2.5v dual cmos (complementary) frequency code a oe active high b oe active low 2 option code: stability & apr frequency code frequency description mxxxxxx f out < 1 mhz xmxxxxx 1 mhz ? f out < 10 mhz m 10 mh ? f 100 mh temp stability kv minimum apr 3.3 v 2.5 v a 20ppm 150ppm/v 100ppm 80ppm xx m xxxx 10 mh z ? f out < 100 mh z xxxmxxx 100 mhz ? f out < 250 mhz xxxxxx code if frequency requires >6 digit resolution b 20ppm 120ppm/v 80ppm 50ppm c 20ppm 90ppm/v 50ppm 30ppm d 20ppm 60ppm/v 30ppm not supported
SI515 rev. 1.0 15 4. package outline di agram: 5 x 7 mm, 6-pin figure 3 illustrates the package details for the SI515. table 14 lists the val ues for the dimensions shown in the illustration. figure 3. SI515 outline diagram table 14. package diagram dimensions (mm) dimension min nom max a 1.50 1.65 1.80 b 1.30 1.40 1.50 c 0.50 0.60 0.70 d 5.00 bsc. d1 4.30 4.40 4.50 e 2.54 bsc. e 7.00 bsc. e1 6.10 6.20 6.30 h 0.55 0.65 0.75 l 1.17 1.27 1.37 l1 0.05 0.10 0.15 p 1.80 ? 2.60 r 0.7 ref. aaa 0.15 bbb 0.15 ccc 0.10 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. ?
SI515 16 rev. 1.0 5. pcb land pattern: 5 x 7 mm, 6-pin figure 4 illustrates the 5 x 7 mm pcb land pattern for the si51 5. table 15 lists the values for the dimensions shown in the illustration. figure 4. SI515 pcb land pattern table 15. pcb land pattern dimensions (mm) dimension (mm) c1 4.20 e5.08 x1 1.55 y1 1.95 notes: general 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. all dimensions shown are at maximum materi al condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearanc e between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is pe r the jedec/ipc j-std- 020 specification for small body components.
SI515 rev. 1.0 17 6. package outline diag ram: 3.2 x 5.0 mm, 6-pin figure 5 illustrates the package details for the 3.2 x 5 mm si 510/511. table 16 lists the values for the dimensions shown in the illustration. figure 5. si510/511 outline diagram table 16. package diagram dimensions (mm) dimension min nom max a1.061.171.28 b0.540.640.74 c0.350.450.55 d 3.20 bsc d1 2.55 2.60 2.65 e 1.27 bsc e 5.00 bsc e1 4.35 4.40 4.45 h0.450.550.65 l0.901.001.10 l1 0.05 0.10 0.15 p1.171.271.37 r0.32 ref aaa 0.15 bbb 0.15 ccc 0.10 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. ?
SI515 18 rev. 1.0 7. pcb land pattern: 3.2 x 5.0 mm, 6-pin figure 6 illustrates the recomme nded 3.2 x 5 mm pcb land pattern for the si 515. table 17 lists the values for the dimensions shown in the illustration. figure 6. SI515 pcb land pattern table 17. pcb land pattern dimensions (mm) dimension (mm) c1 2.60 e1.27 x1 0.80 y1 1.70 notes: general 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per th e ansi y14.5m-199 4 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electro-polis hed stencil with trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the jedec/ipc j-st d-020 specification for small body components. ?
SI515 rev. 1.0 19 8. top marking use the part number config uration utility located at: www.silabs.com/vcxopartnumber to cross-re ference the mark code to a specific device configuration. 8.1. SI515 top marking 8.2. top marking explanation mark method: laser line 1 marking: 5 = SI515 ccccc = mark code 5ccccc line 2 marking: tttttt = assembly manufacturing code tttttt line 3 marking: pin 1 indicator. circle with 0.5 mm diameter; left-justified yy = year. ww = work week. characters correspond to the year and work week of package assembly. yyww 5ccccc ttt t t t yyww
SI515 20 rev. 1.0 d ocument c hange l ist revision 0.9 to revision 1.0 ? updated table 1 on page 4. ?? updates to supply current typical and maximum values for cmos, lvds, lvpecl and hcsl. ?? cmos frequency test condition corrected to 100 mhz. ?? updates to oe vih minimum and vil maximum values. ? updated table 3 on page 5. ?? dual cmos nominal frequency maximum added. ?? disable time maximum values updated. ?? enable time parameter added. ? updated table 4 on page 6. ?? cmos output rise / fall time typical and maximum values updated. ?? lvpecl/hcsl output rise / fall time maximum value updated. ?? lvpecl output swing maximum value updated. ?? lvds output common mode typical and maximum values updated. ?? hcsl output swing maximum value updated. ?? duty cycle minimum and maxi mum values tightened to 48/52%. ? updated table 5 on page 7. ?? phase jitter test condition, typical and maximum value updated. ?? phase noise typical values updated. ?? additive rms jitter due to external power supply noise typical values updated. ? added tables 6, 7, 8 for lvds, hcsl, cmos and dual cmos operations. ? added note to figure 2 clarifying cmos and dual cmos maximum frequency. ? updated figure 5 outline diagram to correct pinout. ? updated ?8. top marking? section and moved to page 19.
SI515 rev. 1.0 21 n otes :
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